Although bipolar semiconductor devices have a lower integration density and higher manufacturing costs than MOS devices, bipolar integrated circuits are employed in a variety of high speed signal processing applications because of their relatively small propagation delay. With the development of polysilicon manufacturing techniques (sometimes referred to as PSA), the development of bipolar technology as seen an increase in integration density. However, in a conventional polysilicon process, the resulting physical/electronic properties of the bipolar device may vary widely from device-to-device and from run-to-run, so that the yield is not predictable and, moreover, the integration density is often reduced.
FIG. 1 shows a cross sectional illustration of an NPN bipolar transistor that is manufactured in accordance with a conventional polysilicon manufacturing process. Specifically, on the surface of a P-type silicon substrate 101, an N-type conductivity layer 102, which is to serve as the collector of the transistor, is epitaxially formed. A P-type extrinsic base region 103 and a P-type intrinsic base region 104 are formed in the epitaxial collector layer 102. In the upper surface of the intrinsic P-type base region 104, an N+type emitter region 105 is formed. Surrounding the extrinsic base region 103 is an isolating dielectric (oxide) 106. Contact with the extrinsic P-type base region 103 is derived by way of a P doped polysilicon layer 107 formed atop the extrinsic base region 103 and the isolating oxide layer 106. A polysilicon oxide film 108 is formed atop the P-type polysilicon layer 107, exposing the upper surface of the emitter region 105. Formation of an ohmic contact with the emitter region 105 at the surface of base region 104 is effected by way an N. doped polysilicon layer 109, which is contiguous with the polysilicon oxide film 108 and the top surface of the emitter region 105 in the upper portion of base layer 104.
In a polysilicon-processed bipolar transistor as shown in FIG. 1, one of the most important considerations is the control of the relatively shallow junction depth (on the order of 0.l .mu.m-0.2 .mu.m) of the junction formed between the emitter region 105 and base region 104. Through the use of the polysilicon layer 109, it is possible to form a very shallow emitter region, which not only reduces the depth of the base emitter junction, but significantly reduces the junction capacitance. In addition, inter-electrode separation is reduced while, at the same time, resistance is decreased, thereby significantly lowering the RC time constant of the junction and thereby enhancing the speed of operation of the resulting bipolar transistor.
In the course of vapor deposition of the polysilicon layer, there is an unequal growth of oxide of 15-20.ANG. thickness from the surface of the silicon, which cannot be removed due to the previous exposure of the boundary surface of the silicon substrate and the polysilicon layer. Consequently, the polysilicon process suffers from a number of defects including an increase in resistance of the emitter contact and the concentration of current flow at the emitter contact which, in turn, degrades the transconductance associated with the partial breakdown of the oxide caused by the current flow. In order to reduce this degradation problem, the emitter contact resistance should be decreased to a low a value as possible. There is a need, therefore, of a mechanism for reducing the emitter contact resistance in order that the emitter area itself can be reduced and thereby the integration density enhanced.
FIG. 2 is an enlarged view of the boundary surface region 110 between the polysilicon layer 109 and the emitter region within the surface portion of the substrate shown in FIG. 1. Specifically, FIG. 2 illustrates the P-type intrinsic base region 104, the N+emitter 105, polysilicon layer 109 doped with an N-type impurity (e.g. arsenic) and a native oxide region 111. Grain boundaries within the polysilicon layer 109 are shown at 112 while a breakdown region in portions of the native oxide 111 due to arsenic diffusion are shown at 113. A further degradation in the native oxide 111 is shown at 114, resulting from the flow of emitter current therethrough. As shown in FIG. 2, the thickness of the native oxide layer 111 is not only uneven, but it is punctuated by anomalies 113 and 114 resulting from dopant (e.g. arsenic) diffusion and current flow. Consequently,, across the surface of emitter region 105 at the boundary with the overlying polysilicon layer 109 there is a substantial variation in the emitter contact resistance.
Conventional efforts to obviate the above described defects at the boundary surface between the polysilicon layer and the emitter contact region have involved two approaches. In the first instance, in order to reduce the resistance of the emitter contact, high temperature anneal (on the order of 1150.degree. C.) and high density (greater than 10.sup.21 cm.sup.-3) surface treatment for the purpose of removing the uneven oxide layer have been proposed. With this approach, the thin surface oxide layer 111 was caused to effectively disintegrate. This was followed by recrystallizing the surface for the polysilicon contact which effectively causes the emitter to spread over a distance equal to the thickness of the polysilicon.
In accordance with the second approach, a chemical oxide or silicon nitride layer is grown to a thickness of 20-30.ANG. as a substitute for the defective oxide.
Although the first approach (destruction of the oxide layer through high temperature anneal and high density bombardment) is capable of reducing the emitter contact resistance, it suffers from crystallization defects which lead to high impurity density and variation in junction depth due to the high temperature treatment. In addition, during the process, silicon carbide is formed at the boundary surface, which effectively prevents a further decrease in resistance. In the second approach, of forming the substitute, or replacement, dielectric for the defective oxide portions prevents an effective reduction in contact area and thereby prevents an increase in integration density.